A through-silicon via (TSV) is a vertical electrical connection passing through a silicon wafer or die. TSV technology is important in creating 3-dimensional (3D) packages and 3D integrated circuits. A 3D package, e.g. system in package, chip stack multi-chip module (MCM), etc., contains two or more chips (integrated circuits) stacked vertically so that they occupy less space.
In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra interposer layer between the chips. In some new 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package.
A 3D integrated circuit is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they are packaged as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small footprint. In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation.
However, interface failure between TSV and interconnect pad is problematic. For example, copper TSV connected to an aluminum interconnect pad suffers high thermal stress because of temperature coefficient difference and the large thickness of copper. The failure location is typically at an interface between Cu and Al/AlCu. The cause of the failure is Cu delamination induced by Joule heating or higher temperature.